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cy7c64215 encore? iii full-speed usb controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-08036 rev. *l revised january 16, 2014 features powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? two 8 8 multiply, 32-bit accumulate ? 3.15 to 5.25-v operating voltage ? usb 2.0 usb-if certified. tid# 40000110 ? commercial operating temperature range: 0 c to +70 c ? industrial operating temperature range: ?40 c to +85 c advanced peripherals (encore? iii blocks) ? six analog encore iii blocks provide: ? up to 14-bit incremental and delta sigma analog-to-digital converters (adcs) ? programmable threshold comparator ? four digital encore iii blocks provide: ? 8-bit and 16-bit pulse width modulators (pwms), timers, and counters ?i 2 c master ? spi master or slave ? full-duplex universal asynch ronous receiver-transmitter (uart) ? cyfisnp modules to talk to cypress cyfi? radio complex peripherals by combining blocks full-speed usb (12 mbps) ? four unidirectional endpoints ? one bidirectional control endpoint ? dedicated 256-byte buffer ? no external crystal required ? operational at 3.15 v to 3.5 v or 4.35 v to 5.25 v flexible on-chip memory ? 16 kb flash program storage 50,000 erase/write cycles ? 1 kb sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all general purpose i/os (gpios) ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpios ? configurable interrupt on all gpios precision, programmable clocking ? internal 4% 24- and 48-mhz oscillator with support for external clock oscillator ? internal oscillator for watchdog and sleep ? .25% accuracy for usb with no external components additional system resources ? inter-integrated circuit (i 2 c) slave, master, and multimaster to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc ? designer ? ) ? full-featured, in-circuit emulator and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory encore iii core block diagram errata: for information on silicon errata, see ?errata? on page 40. details include trigger conditions, devices affected, and proposed workaround.
cy7c64215 document number: 38-08036 rev. *l page 2 of 45 contents applications ...................................................................... 3 encore iii functional overview ...................................... 3 encore iii core .......................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 4 additional system resources ..................................... 4 encore iii device characteri stics .............................. 4 getting started .................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 development tools .......................................................... 5 psoc designer software subsyst ems .......... .............. 5 designing with psoc designer ....................................... 6 select components ..................................................... 6 configure components .......... .............. .............. ......... 6 organize and connect .............. .............. ........... ......... 6 generate, verify, and debug ....................................... 6 pin information ................................................................. 7 56-pin part pinout ....................................................... 7 28-pin part pinout ....................................................... 8 register reference ........................................................... 9 register mapping tables ............................................ 9 register map bank 0 table: user space ................. 10 register map bank 1 table: configuration space ... 11 electrical specifications ................................................ 12 absolute maximum ratings .... ................................... 13 operating temperature ............................................. 13 dc electrical characteristics ..................................... 14 ac electrical characteristics ..................................... 24 packaging information ................................................... 30 package diagrams .................................................... 30 thermal impedance .................................................. 32 solder reflow peak temperat ure ............................. 32 ordering information ...................................................... 33 ordering code definitions ..... .................................... 33 acronyms ........................................................................ 34 acronyms used ......................................................... 34 reference documents .................................................... 34 document conventions ................................................. 35 units of measure ....................................................... 35 numeric conventions ............ .................................... 35 glossary .......................................................................... 35 errata ............................................................................... 40 part numbers affected .............................................. 40 cy7c64215 qualification status ............ ........... ........ 40 cy7c64215 errata summary .. ............... ........... ........ 40 document history page ................................................. 43 sales, solutions, and legal information ...................... 45 worldwide sales and design s upport ......... .............. 45 products .................................................................... 45 psoc? solutions ...................................................... 45 cypress developer community ................................. 45 technical support ................. .................................... 45
cy7c64215 document number: 38-08036 rev. *l page 3 of 45 applications pc human interface devices ? mouse (optomechanical, optical, trackball) ? keyboards ? joysticks gaming ? game pads ? console keyboards general purpose ? barcode scanners ? pos terminal ? consumer electronics ? to y s ? remote controls ? usb to serial encore iii functional overview the encore iii is based on the flexible psoc architecture and is a full-featured, full-speed (1 2-mbps) usb part. configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of c onsumer, and communication applica- tions. this architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in both 28-pin ssop and 56-pin qfn packages. encore iii architecture, as illustrated in the ?block diagram? on page 1, is comprised of four main areas: encore iii core, digital system, analog system , and system resources including a full-speed usb port. configurable global busing enables all the device resources to combine into a complete custom system. the encore iii cy7c64215 can have up to seven i/o ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. encore iii core the encore iii core is a powerful engine that supports a rich feature set. the core includes a cpu, memory, clocks, and configurable gpios. the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four-million instructions per second (mips) 8-bit harvard-architecture microprocessor. the cpu uses an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. program execution is timed and protected using the included sleep and watchdog timers (wdt). memory encompasses 16 kb of flash for program storage, 1 kb of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, enabling customized software ip protection. encore iii incorporates flexible internal clock generators, including a 24-mhz internal main oscillator (imo) accurate to 8% over temperature and voltage as well as an option for an external clock oscillator (eco). usb op eration requires the osc lock bit of the usb_cr0 register to be set to obtain imo accuracy to.25%. the 24-mhz imo is doubled to 48 mhz for use by the digital system, if needed. the 48-mhz clock is required to clock the usb block and must be enabled for communication. a low-power 32-khz internal low-speed osc illator (ilo) is provided for the sleep timer and wdt. the clocks, together with programmable clock dividers (system resource), provide flex ibility to integrate almost any timing requirement in to encore iii. in usb systems, the imo self-tunes to 0.25% accuracy for usb communication. the extended temperature range for the industrial operating range (?40 c to +85 c) requires the use of an eco, which is only available on the 56-pin qfn package. encore iii gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, enabli ng great flexibility in external interfacing. every pin also has capability to generate a system interrupt on high-level, low-level, and change from last read. the digital system the digital system is composed of four digital enco re iii blocks. each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram the following digital configurations can be built from the blocks: pwms, timers, and counters (8-bit and 16-bit) uart 8-bit with selectable parity spi master and slave i 2 c master rf interface: interface to cypress cyfi radio the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also enable signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital encore iii block array to a nalog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7
cy7c64215 document number: 38-08036 rev. *l page 4 of 45 the analog system the analog system is composed of six configurable blocks, comprised of an opamp circuit enabling the creation of complex analog signal flows. analog peripherals are very flexible and are customized to support specif ic application requirements. encore iii analog function supports the analog-to-digital converters (with 6- to 14-bit resolution, selectable as incre- mental, and delta-sigma) and programmable threshold comparator). analog blocks are arranged in two columns of three, with each column comprising one continuous time (ct) - ac b00 or ac b01 - and two switched capacitor (sc) - asc10 and asd20 or asd11 and asc21 - blocks, as shown in figure 2 . figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin in ports 0 to 5. pins are connected to the bus individually or in any combi- nation. the bus also connects to the analog system for analysis with comparators and analog-to-digital converters. it is split into two sections for simultaneous dual-channel processing. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. additional system resources system resources provide additional capability useful to complete systems. additional re sources include a multiplier, decimator, low voltage detection, and power-on reset. brief statements describing the merits of each resource follow. full-speed usb (12 mbps) with five configurable endpoints and 256 bytes of ram. no external components required except two series resistors. industrial temperature operating range for usb requires an external clock oscillator. two multiply accumulates (macs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta-sigma adcs. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks are routed to both the digital and analog systems. the i 2 c module provides 100- and 400-khz communication over two wires. slave, master, and multimaster modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced power-on reset (por) circuit elimi- nates the need for a system supervisor. encore iii device characteristics encore iii devices have four digital blocks and six analog blocks. the following table lists the resources available for specific encore iii devices. acb00 acb01 block ar r a y array input configuration aci1[1:0] asd20 aci0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin ref in bandgap ref hi ref lo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference all io (except port 7) analog mux bus table 1. encore iii device characteristics part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy7c64215 28 pin up to 22 1 4 22 2 2 6 1k 16k cy7c64215 56 pin up to 50 1 4 48 2 2 6 1k 16k
cy7c64215 document number: 38-08036 rev. *l page 5 of 45 getting started the quickest path to understanding the encore iii silicon is by reading this datasheet and using the psoc designer integrated development environment (ide). this datasheet is an overview of the encore v integrated circ uit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requir ements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated applicatio n programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a ba se device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are adcs, dacs, amp lifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing.
cy7c64215 document number: 38-08036 rev. *l page 6 of 45 c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays onl ine, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in -circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select user modules 2. configure user modules 3. organize and connect 4. generate, verify, and debug select components psoc designer provides a library of pre-built, pre-tested hardware peripheral components called "user modules". user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure components each of the user modules you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your part icular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parame ters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operat ion of the user module and provide performance specificatio ns. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the "generate configuration files" step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
cy7c64215 document number: 38-08036 rev. *l page 7 of 45 pin information 56-pin part pinout the cy7c64215 encore iii device is available in a 56-pin package which is listed and illustrated in the following table. every port pin (labeled ?p?) is capable of digital i/o. however, v ss and v dd are not capable of digital i/o. table 2. 56-pin part pinout (qfn-mlf sawn) [1] pin no. type name description figure 3. cy7c64215 56-pin encore iii device digital analog 1 i/o i, m p2[3] direct switched capacitor block input. 2 i/o i, m p2[1] direct switched capacitor block input. 3 i/o m p4[7] 4 i/o m p4[5] 5 i/o m p4[3] 6 i/o m p4[1] 7 i/o m p3[7] 8 i/o m p3[5] 9 i/o m p3[3] 10 i/o m p3[1] 11 i/o m p5[7] 12 i/o m p5[5] 13 i/o m p5[3] 14 i/o m p5[1] 15 i/o m p1[7] i 2 c serial clock (scl). 16 i/o m p1[5] i 2 c serial data (sda). 17 i/o m p1[3] 18 i/o m p1[1] i 2 c scl, issp-sclk. 19 power v ss ground connection. 20 usb d+ 21 usb d- 22 power v dd supply voltage. 23 i/o p7[7] 24 i/o p7[0] 25 i/o m p1[0] i 2 c sda, issp-sdata. 26 i/o m p1[2] 27 i/o m p1[4] optional external clock input extclk. 28 i/o m p1[6] 29 i/o m p5[0] pin no. type name description 30 i/o m p5[2] digital analog 31 i/o m p5[4] 44 i/o m p2[6] external voltage reference (vref) input. 32 i/o m p5[6] 45 i/o i, m p0[0] analog column mux input. 33 i/o m p3[0] 46 i/o i, m p0[2] analog column mux input and column output. 34 i/o m p3[2] 47 i/o i, m p0[4] analog column mux input and column output. 35 i/o m p3[4] 48 i/o i, m p0[6] analog column mux input. 36 i/o m p3[6] 49 power v dd supply voltage. 37 i/o m p4[0] 50 power v ss ground connection. 38 i/o m p4[2] 51 i/o i, m p0[7] analog column mux input. 39 i/o m p4[4] 52 i/o i/o, m p0[5] analog column mux input and column output 40 i/o m p4[6] 53 i/o i/o, m p0[3] analog column mux input and column output. 41 i/o i, m p2[0] direct switched capacitor block input. 54 i/o i, m p0[1] analog column mux input. 42 i/o i, m p2[2] direct switched capacitor block input. 55 i/o m p2[7] 43 i/o m p2[4] external analog ground (agnd) input. 56 i/o mp2[5] legend a = analog, i = input, o = output, and m = analog mux input. note 1. the center pad on the qfn-mlf package should be connected to ground (v ss ) for best mechanical, thermal, and electric al performance. if not connected to ground, it should be electrically floated an d not connected to any other signal. qfn-mlf ( top view ) a, i, m, p2[3] a, i, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- v dd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m v dd v ss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2] , a , i , m p2[0] , a , i , m p4[6] , m p4[4] , m p4[2] , m p4[0] , m p3[6] , m p3[4] , m p3[2] , m p3[0] , m p5[6] , m p5[4] , m p5[2] , m p5[0] , m 42 41 40 39 38 37 36 35 34 33 32 31 30 29
cy7c64215 document number: 38-08036 rev. *l page 8 of 45 28-pin part pinout the cy7c64215 encore iii device is available in a 28-pin package which is listed and illustrated in the following table. every port pin (labeled with a ?p?) is capable of digital i/o. however, v ss and v dd are not capable of digital i/o. table 3. 28-pin part pinout (ssop) pin no. type name description figure 4. cy7c64215 28-pin encore iii device digital analog 1 power gnd ground connection. 2 i/o i, m p0[7] analog column mux input. 3 i/o i/o,m p0[5] analog column mux input and column output. 4 i/o i/o,m p0[3] analog column mux input and column output. 5 i/o i,m p0[1] analog column mux input. 6 i/o m p2[5] 7 i/o m p2[3] direct switched capacitor block input. 8 i/o m p2[1] direct switched capacitor block input. 9 i/o m p1[7] i 2 c scl 10 i/o m p1[5] i 2 c sda 11 i/o m p1[3] 12 i/o m p1[1] i 2 c scl, issp-sclk. 13 power gnd ground connection. 14 usb d+ 15 usb d- 16 power v dd supply voltage. 17 i/o m p1[0] i 2 c scl, issp-sdata. 18 i/o m p1[2] 19 i/o m p1[4] 20 i/o m p1[6] 21 i/o m p2[0] direct switched capacitor block input. 22 i/o m p2[2] direct switched capacitor block input. 23 i/o m p2[4] external analog ground (agnd) input. 24 i/o m p0[0] analog column mux input. 25 i/o m p0[2] analog column mux input and column output. 26 i/o m p0[4] analog column mux input and column output. 27 i/o m p0[6] analog column mux input. 28 power v dd supply voltage. legend a = analog, i = input, o = output, and m = analog mux input. ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vdd p0[6], ai p0[4], ai p0[2], ai p0[0], ai p2[4] p2[2], ai p2[0], ai p1[6] p1[4] p1[2] p1[0], i2c sda vdd d- vss ai, p0[7] aio, p0[5] aio, p0[3] ai, p0[1] p2[5] ai, p2[3] ai, p2[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, p1[1] vss d+ v dd v dd
cy7c64215 document number: 38-08036 rev. *l page 9 of 45 register reference the register conventions specific to this section are listed in the following table . register mapping tables the encore iii device has a total register address space of 512 bytes. the register space is re ferred to as i/o space and is divided into two banks, bank 0 and bank 1. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set to ?1?, the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. table 4. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy7c64215 document number: 38-08036 rev. *l page 10 of 45 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw pma0_dr 40 rw asc10cr0 80 rw c0 prt0ie 01 rw pma1_dr 41 rw asc10cr1 81 rw c1 prt0gs 02 rw pma2_dr 42 rw asc10cr2 82 rw c2 prt0dm2 03 rw pma3_dr 43 rw asc10cr3 83 rw c3 prt1dr 04 rw pma4_dr 44 rw asd11cr0 84 rw c4 prt1ie 05 rw pma5_dr 45 rw asd11cr1 85 rw c5 prt1gs 06 rw pma6_dr 46 rw asd11cr2 86 rw c6 prt1dm2 07 rw pma7_dr 47 rw asd11cr3 87 rw c7 prt2dr 08 rw usb_sof0 48 r 88 c8 prt2ie 09 rw usb_sof1 49 r 89 c9 prt2gs 0a rw usb_cr0 4a rw 8a ca prt2dm2 0b rw usbio_cr0 4b # 8b cb prt3dr 0c rw usbio_cr1 4c rw 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw ep1_cnt1 4e # 8e ce prt3dm2 0f rw ep1_cnt 4f rw 8f cf prt4dr 10 rw ep2_cnt1 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw ep2_cnt 51 rw asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw ep3_cnt1 52 # asd20cr2 92 rw d2 prt4dm2 13 rw ep3_cnt 53 rw asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw ep4_cnt1 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw ep4_cnt 55 rw asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw ep0_cr 56 # asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw ep0_cnt 57 # asc21cr3 97 rw i2c_scr d7 # 18 ep0_dr0 58 rw 98 i2c_dr d8 rw 19 ep0_dr1 59 rw 99 i2c_mscr d9 # 1a ep0_dr2 5a rw 9a int_clr0 da rw 1b ep0_dr3 5b rw 9b int_clr1 db rw prt7dr 1c rw ep0_dr4 5c rw 9c int_clr2 dc rw prt7ie 1d rw ep0_dr5 5d rw 9d int_clr3 dd rw prt7gs 1e rw ep0_dr6 5e rw 9e int_msk3 de rw prt7dm2 1f rw ep0_dr7 5f rw 9f int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed . # access is bit specific.
cy7c64215 document number: 38-08036 rev. *l page 11 of 45 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw pma0_wa 40 rw asc10cr0 80 rw usbio_cr2 c0 rw prt0dm1 01 rw pma1_wa 41 rw asc10cr1 81 rw usb_cr1 c1 # prt0ic0 02 rw pma2_wa 42 rw asc10cr2 82 rw prt0ic1 03 rw pma3_wa 43 rw asc10cr3 83 rw prt1dm0 04 rw pma4_wa 44 rw asd11cr0 84 rw ep1_cr0 c4 # prt1dm1 05 rw pma5_wa 45 rw asd11cr1 85 rw ep2_cr0 c5 # prt1ic0 06 rw pma6_wa 46 rw asd11cr2 86 rw ep3_cr0 c6 # prt1ic1 07 rw pma7_wa 47 rw asd11cr3 87 rw ep4_cr0 c7 # prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf prt4dm0 10 rw pma0_ra 50 rw 90 gdi_o_in d0 rw prt4dm1 11 rw pma1_ra 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw pma2_ra 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw pma3_ra 53 rw asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw pma4_ra 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw pma5_ra 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw pma6_ra 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw pma7_ra 57 rw asc21cr3 97 rw d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw prt7dm0 1c rw 5c 9c dc prt7dm1 1d rw 5d 9d osc_go_en dd rw prt7ic0 1e rw 5e 9e osc_cr4 de rw prt7ic1 1f rw 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 rw a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac mux_cr4 ec rw dcb03in 2d rw tmp_dr1 6d rw ad mux_cr5 ed rw dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
cy7c64215 document number: 38-08036 rev. *l page 12 of 45 electrical specifications this section presents the dc and ac electrical specifications of the cy7c64215 encore iii. for the most up-to-date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/go/usb . specifications are valid for ?40 c < t a < 85 c and t j < 100 c, except where noted. specificat ions for devices running at greater than 12 mhz are valid for ?40 c < t a < 70c and t j < 82 c. figure 5. voltage versus cpu frequency cpu frequency vdd voltage (v) 5.25 4.35 3.50 3.15 4.75 93 khz 12 mhz 24 mhz valid operating region valid operating region valid operating region [2] note 2. this is a valid operating region for the cpu, but usb hardware is non functional in the voltage range from 3.50 v to 4.35 v.
cy7c64215 document number: 38-08036 rev. *l page 13 of 45 absolute maximum ratings operating temperature table 5. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 ? +100 c higher storage temperatures reduces data retention time. t baketemp bake temperature ? 125 see package label c ? t baketime bake time see package label ? 72 hours ? t a ambient temperat ure with power applied 0 ? +70 c ? v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v ? v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v ? v io2 dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v ? i mio maximum current into any port pin ?25 ? +50 ma ? i maio maximum current into any port pin configured as an analog driver ?50 ? +50 ma ? esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma ? table 6. operating temperature parameter description min typ max unit notes t ac commercial ambient temperature 0 ? +70 c ? t ai industrial ambient temperature ?40 ? +85 c usb operation requires the use of an external clock oscillator and the 56-pin qfn package. t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see ?thermal impedance? on page 32. the user must limit the power consumption to comply with this requirement.
cy7c64215 document number: 38-08036 rev. *l page 14 of 45 dc electrical characteristics dc chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 7. dc chip-level specifications parameter description min typ max unit notes v dd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 15 on page 22. usb hardware is not functional when v dd is between 3.5 v to 4.35 v. i dd5 supply current, imo = 24 mhz (5 v) ? 14 27 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i dd3 supply current, imo = 24 mhz (3.3 v) ? 8 14 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, analog power = off. i sb sleep [3] (mode) current with por, lvd, sleep timer, and wdt [4] . ? 3 6.5 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, 0 c < t a < 55 c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature [4] . ? 4 25 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a < 70 c, analog power = off. notes 3. errata: when the device operates at4.75 v to 5.25 v and the 3.3-v regulator is enabled, a short low pulse may be created on the dp sig nal line during device wakeup. the 15- to 20-s low pulse of the dp line may be interpreted by the host computer as a deattach or the beginning of a wakeup. f or more details refer to errata on page 40. 4. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled.
cy7c64215 document number: 38-08036 rev. *l page 15 of 45 dc gpio specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc full-speed usb specifications the following table lists guaranteed maximum and minimum specif ications for the voltage and temperature ranges when the imo is selected as system clock: 4.75 v to 5.25 v and 0 c < t a < 70 c, or 3.15 v to 3.5 v and 0 c < t a < 70 c, respectively. the following table lists guaranteed maximum and minimum specif ications for the voltage and temperature ranges when an external clock is selected as the system clock: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 8. dc gpio specifications parameter description min typ max unit notes r pu pull-up resistor 4 5.6 8 k ? ? r pd pull-down resistor 4 5.6 8 k ? ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. i oh high-level source current 10 ? ? ma ? i ol low-level sink current 25 ? ? ma ? v il input low level ? ? 0.8 v v dd = 3.15 to 5.25. v ih input high level 2.1 ? v v dd = 3.15 to 5.25. v h input hysteresis ? 60 ? mv ? i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . table 9. dc full speed (12 mbps) usb specifications parameter description min typ max unit notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) ? (d?) | v cm differential input common mode range 0.8 ? 2.5 v ? v se single-ended receiver threshold 0.8 ? 2.0 v ? c in transceiver capacitance ? ? 20 pf ? i io high z state data line leakage ?10 ? 10 ? a0 v < v in < 3.3 v. r ext external usb series resistor 23 ? 25 ? in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k ? 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 ? including r ext resistor. v crs d+/d? crossover voltage 1.3 ? 2.0 v?
cy7c64215 document number: 38-08036 rev. *l page 16 of 45 dc analog output bu ffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10. 5 v dc analog output buffer specifications parameter description min typ max unit notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv ? tcv osob average input offset voltage drift ? +6 ? ? v/c ? v cmob common mode input voltage range 0.5 ? v dd ? 1.0 v? r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? w w ? v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.1 0.5 v dd + 1.1 ? ? ? ? v v ? v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v ? i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma ? psrr ob supply voltage rejection ratio 53 64 ? db (0.5 v dd ? 1.3) < v out < (v dd ? 2.3). table 11. 3.3 v dc analog output buffer specifications parameter description min typ max unit notes c l load capacitance ? ? 200 pf this specification applies to the external circuit that is being driven by the analog output buffer. v osob input offset voltage (absolute value) ? 3 12 mv ? tcv osob average input offset voltage drift ? +6 ? ? v/c ? v cmob common mode input voltage range 0.5 - v dd ? 1.0 v? r outob output resistance power = low power = high ? ? 1 1 ? ? w w ? v ohighob high output voltage swing (load = 1 k ? to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v ? v olowob low output voltage swing (load = 1 k ? to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v ? i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma ? psrr ob supply voltage rejection ratio 34 64 ? db (0.5 v dd ? 1.0) < v out < (0.5 v dd + 0.9).
cy7c64215 document number: 38-08036 rev. *l page 17 of 45 dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specificat ions are measured through the analog continuous ti me psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power leve ls for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 12. 5-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.229 v dd /2 + 1.290 v dd /2 + 1.346 v v agnd agnd v dd /2 v dd /2 ? 0.038 v dd /2 v dd /2 + 0.040 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.356 v dd /2 ? 1.295 v dd /2 ? 1.218 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.220 v dd /2 + 1.292 v dd /2 + 1.348 v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.357 v dd /2 ? 1.297 v dd /2 ? 1.225 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.221 v dd /2 + 1.293 v dd /2 + 1.351 v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.357 v dd /2 ? 1.298 v dd /2 ? 1.228 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.219 v dd /2 + 1.293 v dd /2 + 1.353 v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.001 v dd /2 + 0.036 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.359 v dd /2 ? 1.299 v dd /2 ? 1.229 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.092 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.064 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.007 p2[4] ? p2[6] + 0.056 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.078 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.063 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.031 p2[4] ? p2[6] + 0.004 p2[4] ? p2[6] + 0.043 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.062 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.032 p2[4] ? p2[6] + 0.003 p2[4] ? p2[6] + 0.038 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.073 p2[4] + p2[6] ? 0.006 p2[4] + p2[6] + 0.062 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.034 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.037 v
cy7c64215 document number: 38-08036 rev. *l page 18 of 45 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.029 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.034 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.024 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.032 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.036 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.022 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.031 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.020 v 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.760 3.884 4.006 v v agnd agnd 2 bandgap 2.522 2.593 2.669 v v reflo ref low bandgap 1.252 1.299 1.342 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.766 3.887 4.010 v v agnd agnd 2 bandgap 2.523 2.594 2.670 v v reflo ref low bandgap 1.252 1.297 1.342 v refpower = medium opamp bias = high v refhi ref high 3 bandgap 3.769 3.888 4.013 v v agnd agnd 2 bandgap 2.523 2.594 2.671 v v reflo ref low bandgap 1.251 1.296 1.343 v refpower = medium opamp bias = low v refhi ref high 3 bandgap 3.769 3.889 4.015 v v agnd agnd 2 bandgap 2.523 2.595 2.671 v v reflo ref low bandgap 1.251 1.296 1.344 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.483 ? p2[6] 2.582 ? p2[6] 2.674 ? p2[6] v v agnd agnd 2 bandgap 2.522 2.593 2.669 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.524 ? p2[6] 2.600 ? p2[6] 2.676 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.490 ? p2[6] 2.586 ? p2[6] 2.679 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.594 2.669 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.523 ? p2[6] 2.598 ? p2[6] 2.675 ? p2[6] v refpower = medium opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.493 ? p2[6] 2.588 ? p2[6] 2.682 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.594 2.670 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.523 ? p2[6] 2.597 ? p2[6] 2.675 ? p2[6] v refpower = medium opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.494 ? p2[6] 2.589 ? p2[6] 2.685 ? p2[6] v v agnd agnd 2 bandgap 2.523 2.595 2.671 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.522 ? p2[6] 2.596 ? p2[6] 2.676 ? p2[6] v table 12. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy7c64215 document number: 38-08036 rev. *l page 19 of 45 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.218 p2[4] + 1.291 p2[4] + 1.354 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.294 p2[4] ? 1.237 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.221 p2[4] + 1.293 p2[4] + 1.358 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.337 p2[4] ? 1.297 p2[4] ? 1.243 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.294 p2[4] + 1.360 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.338 p2[4] ? 1.298 p2[4] ? 1.245 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.221 p2[4] + 1.294 p2[4] + 1.362 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.340 p2[4] ? 1.298 p2[4] ? 1.245 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.513 2.593 2.672 v v agnd agnd bandgap 1.264 1.302 1.340 v v reflo ref low v ss v ss v ss + 0.008 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.514 2.593 2.674 v v agnd agnd bandgap 1.264 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.028 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.514 2.593 2.676 v v agnd agnd bandgap 1.264 1.301 1.340 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.024 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.514 2.593 2.677 v v agnd agnd bandgap 1.264 1.300 1.340 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.021 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.028 4.144 4.242 v v agnd agnd 1.6 bandgap 2.028 2.076 2.125 v v reflo ref low v ss v ss v ss + 0.008 v ss + 0.034 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.032 4.142 4.245 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.025 v refpower = medium opamp bias = high v refhi ref high 3.2 bandgap 4.034 4.143 4.247 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.021 v refpower = medium opamp bias = low v refhi ref high 3.2 bandgap 4.036 4.144 4.249 v v agnd agnd 1.6 bandgap 2.029 2.076 2.126 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.019 v table 12. 5-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units
cy7c64215 document number: 38-08036 rev. *l page 20 of 45 table 13. 3.3-v dc analog reference specifications reference arf_cr [5:3] reference power settings symbol reference description min typ max units 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.200 v dd /2 + 1.290 v dd /2 + 1.365 v v agnd agnd v dd /2 v dd /2 ? 0.030 v dd /2 v dd /2 + 0.034 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.346 v dd /2 ? 1.292 v dd /2 ? 1.208 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.196 v dd /2 + 1.292 v dd /2 + 1.374 v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.031 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.349 v dd /2 ? 1.295 v dd /2 ? 1.227 v refpower = medium opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.204 v dd /2 + 1.293 v dd /2 + 1.369 v v agnd agnd v dd /2 v dd /2 ? 0.030 v dd /2 v dd /2 + 0.030 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.351 v dd /2 ? 1.297 v dd /2 ? 1.229 v refpower = medium opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.189 v dd /2 + 1.294 v dd /2 + 1.384 v v agnd agnd v dd /2 v dd /2 ? 0.032 v dd /2 v dd /2 + 0.029 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.353 v dd /2 ? 1.297 v dd /2 ? 1.230 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.105 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.095 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.035 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.053 v refpower = high opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.094 p2[4] + p2[6] ? 0.005 p2[4] + p2[6] + 0.073 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.033 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.042 v refpower = medium opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.094 p2[4] + p2[6] ? 0.003 p2[4] + p2[6] + 0.075 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.035 p2[4] ? p2[6] p2[4] ? p2[6] + 0.038 v refpower = medium opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.095 p2[4] + p2[6] ? 0.003 p2[4] + p2[6] + 0.080 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.038 p2[4] ? p2[6] p2[4] ? p2[6] + 0.038 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.119 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.022 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.131 v dd ? 0.004 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.021 v refpower = medium opamp bias = high v refhi ref high v dd v dd ? 0.111 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.028 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high v dd v dd ? 0.128 v dd ? 0.003 v dd v v agnd agnd v dd /2 v dd /2 ? 0.029 v dd /2 v dd /2 + 0.029 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.019 v 0b011 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ?
cy7c64215 document number: 38-08036 rev. *l page 21 of 45 dc analog encore iii block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 0b100 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.214 p2[4] + 1.291 p2[4] + 1.359 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.292 p2[4] ? 1.200 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.219 p2[4] + 1.293 p2[4] + 1.357 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.335 p2[4] ? 1.295 p2[4] ? 1.243 v refpower = medium opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.294 p2[4] + 1.356 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.337 p2[4] ? 1.296 p2[4] ? 1.244 v refpower = medium opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.224 p2[4] + 1.295 p2[4] + 1.355 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.339 p2[4] ? 1.297 p2[4] ? 1.244 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.510 2.595 2.655 v v agnd agnd bandgap 1.276 1.301 1.332 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.031 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.513 2.594 2.656 v v agnd agnd bandgap 1.275 1.301 1.331 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.021 v refpower = medium opamp bias = high v refhi ref high 2 bandgap 2.516 2.595 2.657 v v agnd agnd bandgap 1.275 1.301 1.331 v v reflo ref low v ss v ss v ss + 0.003 v ss + 0.017 v refpower = medium opamp bias = low v refhi ref high 2 bandgap 2.520 2.595 2.658 v v agnd agnd bandgap 1.275 1.300 1.331 v v reflo ref low v ss v ss v ss + 0.002 v ss + 0.015 v 0b111 all power settings. not allowed for 3.3 v. ?? ? ? ? ? ? table 13. 3.3-v dc analog reference specifications (continued) reference arf_cr [5:3] reference power settings symbol reference description min typ max units table 14. dc analog encore iii block specifications parameter description min typ max unit notes r ct resistor unit value (ct) ? 12.2 ? k ? ? c sc capacitor unit value (sc) ? 80 ? ff ?
cy7c64215 document number: 38-08036 rev. *l page 22 of 45 dc por and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. note the bits porlev and vm in the following table refer to bits in the vlt_cr register. see the psoc ? technical reference manual for more information on the vlt_cr register. table 15. dc por and lvd specifications parameter description min typ max unit notes v ppor0r [5] v ppor1r [5] v ppor2r [5] v dd value for ppor tr ip (posit ive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v ? v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v ? v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv ? v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [6] 3.08 3.20 4.08 4.57 4.74 [7] 4.82 4.91 v v v v v v v v ? notes 5. errata: when vdd of the device is pulled below ground just before power on , the first read from each 8k flash page may be corrupted. t his issue does not affect flash page 0 because it is the selected page upon reset. for more details in errata on page 40. 6. always greater than 50 mv above ppor (porlev = 00) for falling supply. 7. always greater than 50 mv above ppor (porlev = 10) for falling supply.
cy7c64215 document number: 38-08036 rev. *l page 23 of 45 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 16. dc programming specifications parameter description min typ max unit notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.15 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 15 30 ma ? v ilp input low voltage during programming or verify ? ? 0.8 v? v ihp input high voltage during programming or verify 2.1 ? ? v? i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? v ss + 0.75 v? v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v? flash enpb flash endurance (per block) 50,000 [8] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years ? table 17. dc i 2 c specifications [10] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 3.15 v ?? v dd ?? 3.6 v ? ? 0.25 v dd v 4.75 v ?? v dd ?? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 3.15 v ?? v dd ?? 5.25 v notes 8. the 50,000 cycle flash endurance per block will only be guaran teed if the flash is operating within one voltage range. voltag e ranges are 3.0v to 3.6v and 4.75v to 5.25v. 9. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operatio ns on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 for more information. 10. all gpios meet the dc gpio v il and v ih specifications found in the dc gp io specifications sections. the i 2 c gpio pins also meet the mentioned specifications.
cy7c64215 document number: 38-08036 rev. *l page 24 of 45 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 18. ac chip-level specifications parameter description min typ max unit notes f imo245v imo frequency for 24 mhz (5 v) 23.04 24 24.96 [11, 12] mhz trimmed for 5 v operation using factory trim values. f imo243v imo frequency for 24 mhz (3.3 v) 22.08 24 25.92 [11,13] mhz trimmed for 3.3 v operation using factory trim values. f imousb imo frequency with usb frequency locking enabled and usb traffic present 23.94 24 24.06 [12] mhz usb operation for system clock source from the imo is limited to 0 c < t a < 70 c. f cpu1 cpu frequency (5 v nominal) 0.090 24 24.96 [11,12] mhz slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.086 12 12.96 [12,13] mhz slimo mode = 0. f blk5 digital psoc block frequency (5 v nominal) 0 48 49.92 [11,12,14] mhz refer to the ac digital block specifica- tions on page 26. f blk3 digital psoc block frequency (3.3 v nominal) 0 24 25.92 [12,14] mhz ? f 32k1 ilo frequency 15 32 64 khz ? f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. dc ilo ilo duty cycle 20 50 80 % ? dc 24m 24-mhz duty cycle 40 50 60 % ? step24m 24-mh trim step size ? 50 ? khz ? fout48m 48-mhz output frequency 46.08 48.0 49.92 [11,13] mhz trimmed. utilizing factory trim values. f max maximum frequency of signal on row input or row output ? ? 12.96 mhz ? sr power_up power supply slew rate ? ? 250 v/ms ? t powerup time from end of por to cpu executing code ? 16 100 ms ? t jit_imo [15] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 1200 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 900 6000 ps n = 32. 24 mhz imo period jitter (rms) ? 200 900 ps notes 11. 4.75 v < v dd < 5.25 v. 12. accuracy derived from internal main oscillator with appropriate trim for v dd range. 13. 3.0 v < v dd < 3.6 v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimming for operation at 3.3 v. 14. see the individual user module data sheets for in formation on maximum frequencies for user modules. 15. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information.
cy7c64215 document number: 38-08036 rev. *l page 25 of 45 ac gpio specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 6. gpio timing diagram ac full speed usb specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 19. ac gpio specifications parameter description min typ max unit notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10%?90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10%?90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10%?90% table 20. ac full-speed (12 mbps) usb specifications parameter description min typ max unit notes t rfs transition rise time 4 ? 20 ns for 50-pf load. t fss transition fall time 4 ? 20 ns for 50-pf load. t rfmfs rise/fall time matching: (t r /t f )90 ? 111 % for 50-pf load. t dratefs full-speed data rate 12 ? 0.25% 12 12 + 0.25% mbps ? tf allf tf alls trisef tr is es 90% 10% gpio pin output voltage
cy7c64215 document number: 38-08036 rev. *l page 26 of 45 ac digital block specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 21. ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.92 mhz v dd < 4.75 v ? ? 25.92 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.92 mhz no capture, v dd < 4.75 v ? ? 25.92 mhz with capture ? ? 25.92 mhz capture pulse width 50 [16] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.92 mhz no enable input, v dd < 4.75 v ? ? 25.92 mhz with enable input ? ? 25.92 mhz enable input pulse width 50 [16] ??ns kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [16] ??ns disable mode 50 [16] ??ns input clock frequency v dd ? 4.75 v ? ? 49.92 mhz v dd < 4.75 v ? ? 25.92 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.92 mhz v dd < 4.75 v ? ? 25.92 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [16] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.92 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.92 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
cy7c64215 document number: 38-08036 rev. *l page 27 of 45 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 22. ac external clock specifications parameter description min typ max unit notes f oscext frequency for usb applications 23.94 24 24.06 mhz usb operation in the extended industrial temperature range (?40 c < t a < 85 c) requires that the syst em clock is sourced from an external clock oscillator. ? duty cycle 47 50 53 % ? ? power-up to imo switch 150 ? ? ? s? table 23. 5 v ac analog output buffer specifications parameter description min typ max unit notes t rob rising settling time to 0.1%, 1 v step, 100-pf load power = low power = high ? ? ? ? 2.5 2.5 ? s ? s ? t sob falling settling time to 0.1%, 1 v step, 100-pf load power = low power = high ? ? ? ? 2.2 2.2 ? s ? s ? sr rob rising slew rate (20% to 80%), 1 v step, 100-pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s ? sr fob falling slew rate (80% to 20%), 1 v step, 100-pf load power = low power = high 0.65 0.65 ? ? ? ? v/ ? s v/ ? s ? bw obss small signal bandwidth, 20 mv pp , 3-db bw, 100-pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz ? bw obls large signal bandwidth, 1 v pp , 3-db bw, 100-pf load power = low power = high 300 300 ? ? ? ? khz khz ? table 24. 3.3 v ac analog output buffer specifications parameter description min typ max unit notes t rob rising settling time to 0.1%, 1 v step, 100-pf load power = low power = high ? ? ? ? 3.8 3.8 ? s ? s ? t sob falling settling time to 0.1%, 1 v step, 100-pf load power = low power = high ? ? ? ? 2.6 2.6 ? s ? s ? sr rob rising slew rate (20% to 80%), 1 v step, 100-pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s ? sr fob falling slew rate (80% to 20%), 1 v step, 100-pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s ? bw obss small signal bandwidth, 20 mv pp , 3db bw, 100-pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz ? bw obls large signal bandwidth, 1 v pp , 3db bw, 100-pf load power = low power = high 200 200 ? ? ? ? khz khz ?
cy7c64215 document number: 38-08036 rev. *l page 28 of 45 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 25. ac programming specifications parameter description min typ max unit notes t rsclk rise time of sclk 1 ? 20 ns ? t fsclk fall time of sclk 1 ? 20 ns ? t ssclk data setup time to falling edge of sclk 40 ? ? ns ? t hsclk data hold time from falling edge of sclk 40 ? ? ns ? f sclk frequency of sclk 0 ? 8 mhz ? t eraseb flash erase time (block) ? 10 ? ms ? t write flash block write time ? 40 ? ms ? t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd ? 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.15 < v dd < 3.5 t eraseall flash erase time (bulk) ? 40 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 100 ms 0c ? t j ? 100 c t program_cold flash block erase + flash block write time ? ? 200 ms ?40 c ? t j ? 0c
cy7c64215 document number: 38-08036 rev. *l page 29 of 45 ac i 2 c specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, or 3.15 v to 3.5 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 7. definition for timi ng for fast-/standa rd-mode on the i 2 c bus table 26. ac characteristics of the i 2 c sda and scl pins for v dd parameter description standard-mode fast-mode unit notes min max min max f scli2c scl clock frequency 0 100 0 400 khz ? t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s? t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s? t highi2c high period of the scl clock 4.0 ?0.6 ? ? s? t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? ? s? t hddati2c data hold time 0 ?0 ? ? s? t sudati2c data setup time 250 ? 100 [17] ?ns? t sustoi2c setup time for st op condition 4.0 ?0.6 ? ? s? t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s? t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns? note 17. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but t he requirement t sudati2c ? 250 ns must then be met. this automatically is the case if the device does not stretch the low period of the scl si gnal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy7c64215 document number: 38-08036 rev. *l page 30 of 45 packaging information this section illustrates the package specification for the cy7c64 215 encore iii, along with the thermal impedance for the packa ge. important note emulation tools may require a larger area on the target pcb than the chip's footprint. fo r a detailed description of the emulation tools' dimensions, refe r to the emulator pod drawings at http://www.cypress.com. package diagrams figure 8. 56-pin qfn (8 8 1.0 mm) 4.5 5.21 e-pad (subcon punch type package) package outline, 001-12921 solderable exposed pad 001-12921 *b
cy7c64215 document number: 38-08036 rev. *l page 31 of 45 figure 9. 56-pin qfn (8 8 1.0 mm) 4.5 5.2 e-pad (sawn) pack age outline, 001-53450 figure 10. 28-pin ssop (210 mils) package outline, 51-85079 001-53450 *d 51-85079 *e
cy7c64215 document number: 38-08036 rev. *l page 32 of 45 thermal impedance solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 27. thermal impedance for the package package typical ? ja [18] 56-pin qfn [19] 20 o c/w 28-pin ssop 96 o c/w table 28. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 56-pin qfn 260 c 20 s 28-pin ssop 260 c 20 s notes 18. t j = t a + power x ? ja 19. to achieve the thermal impedance specifi ed for the qfn package, the center thermal pad should be soldered to the pcb ground plane.
cy7c64215 document number: 38-08036 rev. *l page 33 of 45 ordering information ordering code definitions package ordering code flash size sram (bytes) temperature range 28-pin ssop cy7c64215-28pvxc 16k 1k 0 c to 70 c 28-pin ssop (tape and reel) cy7c64215-28pvxct 16k 1k 0 c to 70 c 56-pin qfn (sawn) commercial CY7C64215-56LTXC 16k 1k 0 c to 70 c 56-pin qfn (sawn) commercial (tape and reel) CY7C64215-56LTXCt 16k 1k 0 c to 70 c 56-pin qfn (sawn) industrial cy7c64215-56ltxi 16k 1k ?40 c to 85 c 56-pin qfn (sawn) industrial (tape and reel) cy7c64215-56ltxit 16k 1k ?40 c to 85 c cy marketing code: 7c64 = encore full-speed usb controller 7c64 company id: cy = cypress xxx - xx xxx package type: pvx: ssop ltx: qfn c/i temperature range: commercial/industrial base part number pin count: 28 = 28 pins, 56 = 56 pins (t) tape and reel
cy7c64215 document number: 38-08036 rev. *l page 34 of 45 acronyms acronyms used the following table lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter pcb printed circuit board api application programming interface pga programmable gain amplifier cpu central processing unit por power-on reset crc cyclic redundancy check ppor precision power-on reset ct continuous time psoc ? programmable system-on-chip? dac digital-to-analog converter pwm pulse-width modulator dc direct current qfn quad flat no leads eeprom electrically erasable programmable read-only memory rf radio frequency gpio general purpose i/o sc switched capacitor ice in-circuit emulator slimo slow imo ide integrated development environment spi? serial peripheral interface ilo internal low speed oscillator sram static random-access memory imo internal main oscillator srom supervisory read-only memory i/o input/output ssop shrink small-outline package issp in-system seri al programming uart universal asynchronous receiver / transmitter lvd low voltage detect usb universal serial bus mac multiply-accumulate wdt watchdog timer
cy7c64215 document number: 38-08036 rev. *l page 35 of 45 document conventions units of measure numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimal. symbol unit of measure symbol unit of measure c degree celsius ms milli-second db decibels mv milli-volts ff femto farad na nanoampere khz kilohertz ns nanosecond k ? kilohm ? ohm mhz megahertz pf picofarad ? a microampere ps picosecond ? s microsecond % percent ? v microvolts v volts ma milli-ampere w watts mm milli-meter glossary active high 5. a logic signal having its asserted state as the logic 1 state. 6. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opam p circuits. these are sc (switched capa citor) and ct (continuous time) blocks. these blocks can be interconn ected to provide adcs, dacs , multi-pole filt ers, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interfac e between a computer applicat ion and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for prog rammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posit ive temperature coefficient of vt with the negative temperature coefficient of vbe, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amp lifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as , for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device.
cy7c64215 document number: 38-08036 rev. *l page 36 of 45 block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved fo r io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to r oute nets with similar routing patterns. 2. a set of signals performing a common function and carry ing similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a period ic signal with a fixed frequency and duty cycle. a clock is sometimes used to synchronize different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is cont rolled by a piezoelectric crystal. typically a piezoelectric crys tal is less sensitive to ambient temperatur e than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communic ations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. glossary (continued)
cy7c64215 document number: 38-08036 rev. *l page 37 of 45 external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volati le technology that provides users with the programmability and data storage of eproms, plus in-system erasability. non- volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it wa s later used as a simple internal bus system for building control electronics. i2c uses only two bi-directional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer progra m, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code exec ution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning t he device to the point in the program w here it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exch anges between two devices. or when devices are cascaded in width, the master device is the one that controls th e timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically include s memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minima l quantity of chips, thus achieving ma ximal possible miniaturization. this in turn, reduces the volume and the cost of the cont roller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. glossary (continued)
cy7c64215 document number: 38-08036 rev. *l page 38 of 45 modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. shift register a memory storage dev ice that sequentially shifts a wo rd either left or right to ou tput a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external inte rface. the controlling device is called the master device. glossary (continued)
cy7c64215 document number: 38-08036 rev. *l page 39 of 45 sram an acronym for static random access memory. a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged until it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (hig h-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modu les also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. register s in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning ?voltage drain.? the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning ?voltage source.? the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy7c64215 document number: 38-08036 rev. *l page 40 of 45 errata this section describes the errata for the encore iii cy7c64215 de vice. the information in this document describes hardware issu es associated with silicon revision a. contact your local cypress sales representative if you have questions. part numbers affected cy7c64215 qualification status product status: in production cy7c64215 errata summary this table defines the errata applicability to available encore iii cy7c64215 family devices. 1. usb interface dp line pulses low when the encore iii device wakes from sleep problem definition when the device operates at 4.75 v to 5.25 v and the 3.3-v regulator is enabl ed, a short low pulse may be created on the dp sig nal line during device wakeup. the 15- to 20-s low pulse of the dp lin e may be interpreted by the host computer as a deattach or t he beginning of a wakeup. parameters affected the bandgap reference voltage used by the 3.3-v regulator decreas es during sleep due to leakage. upon device wakeup, the bandga p is re-enabled and, after a delay for sett ling, the 3.3-v regulator is enabled. on so me devices the 3.3-v regulator used to gene rate the usb dp signal may be enabled before the bandgap is fully stabiliz ed. this can cause a low pulse on the regulator output and dp signal line until the bandgap stabilizes. in applications where v dd is 3.3 v, the regulator is not used and, therefore, the dp low pulse is not generated. trigger condition n/a scope of impact n/a workaround to prevent the dp signal from pulsing low, keep the bandgap enab led during sleep. the most effici ent method is to set the no bu zz bit in the osc_cr0 register. the no buzz bit keeps the bandgap powered and output stable during sleep. setting the no buzz bit results in a nominal 100 a increase in sleep current. leaving the analog reference block enabled during sleep also resolves th is issue because it forces the bandgap to remain enabled. the following example shows how to disable the no buzz bit: assembly m8c_setbank1 or reg[osc_cr0], 0x20 m8c_setbank0 c osc_cr0 |= 0x20; part number silicon revision cy7c64215 a items part number silicon revision fix status usb interface dp line pulses low when the encore iii device wakes from sleep. cy7c64215 a no silicon fix planned. use workaround. invalid flash reads may occur if v dd is pulled to ?0.5 v just before power on. cy7c64215 a pma index register fails to auto-increment with cpu_clock set to sysclk/1 (24 mhz). cy7c64215 a
cy7c64215 document number: 38-08036 rev. *l page 41 of 45 fix status there is no planned silic on fix; use workaround. 2. invalid flash reads may occur if v dd is pulled to ?0.5 v just before power on problem definition when v dd of the device is pulled below ground just before power on, the first read from each 8-kb flash page may be corrupted. this issue does not affect flash page 0 because it is the selected page upon reset. parameters affected when v dd is pulled below ground before power on, an internal flash reference may deviate from its nominal voltage. the reference deviation tends to result in the first flash read from that pa ge returning 0xff. during the first read from each page, the refe rence is reset resulting in all futu re reads returning the correct value. a short delay of 5 s before the first real read provides time for the reference voltage to stabilize. trigger condition n/a scope of impact n/a workaround to prevent an invalid flash read, a dummy read from each flash p age must occur before use of the pages. a delay of 5 s must oc cur after the dummy read and before a real read. the dummy reads occu r as soon as possible and must be located in flash page 0 befo re a read from any other flash page. an example for reading a byte of memory from each flash page is listed below. place it in boot.tpl and boot.asm immediately after the ?start:? label. // dummy read from each 8k flash page // page 1 mova, 0x20 // msb movx, 0x00 // lsb romx // wait at least 5 s movx, 14 loop1: decx jnzloop1 fix status there is no planned silic on fix; use workaround. 3. pma index register fails to auto-increment with cpu_clock set to sysclk/1 (24 mhz) problem definition when the device operates at 4.75 v to 5.25 v and the cpu_clock is set to sysclk/1 (24 mhz), t he usb pma index register may fail to increment automatically when used in an out endpoint configuration at full-s peed. when the application program attempts to u se the breadoutep() functi on, the first byte in the pma buffer is always returned. parameters affected an internal flip-flop hold problem is associated with the index register increment function. a ll reads of the associated ram or iginate from the first byte. the hold problem has no impact on other circuits or functions within the device. trigger condition n/a scope of impact n/a
cy7c64215 document number: 38-08036 rev. *l page 42 of 45 workaround to make certain that the index register properly increments, se t the cpu_clock to sysclk/2 (12 mhz) during the read of the pma buffer. an example for the clock adjustment method follows: psoc designer 4.3 user module workaround : psoc designer release 4.3 and subsequent releases include a revised full-speed usb user module with the revised firmware work around included (see the following example). 24-mhz read pma workaround ;; m8c_setbank1 mov a, reg[osc_cr0] push a and a, 0xf8 ;clear the clock bits (briefly chg the cpu_clk to 3mhz) or a, 0x02 ;will set clk to 12mhz mov reg[osc_cr0],a ;clk is now set at 12mhz m8c_setbank0 .loop: mov a, reg[pma0_dr] ; get the data from the pma space mov [x], a ; save it in data array inc x ; increment the pointer dec [usb_apitemp+1] ; decrement the counter jnz .loop ; wait for count to zero out ;; ;; 24mhz read pma workaround (back to previous clock speed) ;; pop a ;recover previous reg[osc_cr0] value m8c_setbank1 mov reg[osc_cr0],a ;clk is now set at previous value m8c_setbank0 ;; ;; end 24mhz read pma workaround fix status there is no planned silic on fix; use workaround.
cy7c64215 document number: 38-08036 rev. *l page 43 of 45 document history page description title: cy7c64215, encore? iii full-speed usb controller document number: 38-08036 rev. ecn no. submission date orig. of change description of change ** 131325 see ecn xgr new data sheet. *a 385256 see ecn bha changed status from advance information to preliminary. added standard data sheet items. changed part number from cy7c642xx to cy7c64215. *b 2547630 08/04/08 aziel/pyrs operational voltage range for usb specified under ?full speed usb (12mbps)?. cmp_go_en1 register removed as it has no functionality on radon. figure ?cpu frequency? adjusted to show invalid operating region for usb with footnote describing reason. dc electrical characteristic, v dd . note added describing where usb hardware is non-functional. *c 2620679 12/12/08 cmcc/pyrs added package handling information. deleted note regarding link to amkor.com for mlf package dimensions. *d 2717887 06/11/2009 dpt added 56 -pin sawn qfn (8 x 8 mm) package diagram and added CY7C64215-56LTXC part information in the ordering information table. *e 2852393 01/15/2010 bha/xut added table of contents . added external clock oscillator option and industrial temperature information to the features , pin information , electrical specifications , operating temper- ature , dc electrical characteristics , ac electrical characteristics , and ordering information sections. updated dc gpio, ac chip, and ac programming specifications follows: ? replaced tramp (time) with srpower_up (slew rate) specification. ? added i oh , i ol , dcilo, f32k_u, tpowerup, teraseall, tprogram_hot, and tprogram_cold specifications. ? updated v dd ranges on figure 5 and table 8. ? added notes for vm and vdi on table 10. ? removed tr/tf from table 20. update ordering information for: cy7c64215-56lfxct, cy7c64215-28pvxct, cy7c64215-56ltxit tape and reel. updated 28-pin ssop and 56-pin qfn punch and sawn package diagrams. updated copyright and sales, solutions, and legal information urls. *f 2892683 03/15/2010 njf updated cypress website links. added t baketemp and t baketime parameters in absolute maximum ratings . updated ac chip-level specifications removed inactive parts from ordering information updated note in packaging information . *g 3070717 10/25/2010 xut removed reference to cyfispi in features . updated datasheet as per cypress style guide and new datasheet template. *h 3090908 11/19/10 csai updated ac ch ip-level specifications table. added dc i 2 c specification. *i 3143408 01/17/11 njf added dc i 2 c specifications table. added tjit_imo specification, remov ed existing jitter specifications. updated analog reference tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding.
cy7c64215 document number: 38-08036 rev. *l page 44 of 45 *j 3995635 05/09/2013 csai updated packaging information : spec 001-12921 ? changed revision from *a to *b. spec 001-53450 ? changed revision from *b to *c. spec 51-85079 ? changed revision from *d to *e. added errata . *k 4080167 07/29/2013 csai added erra ta footnotes (note 3, 5). updated electrical specifications : updated dc electrical characteristics : updated dc chip-level specifications : added note 3 and referred the same note in ?sleep mode? in description of i sb parameter in ta b l e 7 . updated dc por and lvd specifications : added note 5 and referred the same note in v ppor0 , v ppor1 , v ppor2 parameters in table 15 . updated reference documents : removed references of spec 001-17 397 and spec 001-14503 as these specs are obsolete. updated in new template. *l 4247931 01/16/2014 csai updated packaging information : spec 001-53450 ? changed revision from *c to *d. completing sunset review. document history page (continued) description title: cy7c64215, encore? iii full-speed usb controller document number: 38-08036 rev. ecn no. submission date orig. of change description of change
document number: 38-08036 rev. *l revised january 16, 2014 page 45 of 45 psoc designer? and encore? are trademarks and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c64215 ? cypress semiconductor corporation, 2007-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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